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• » Visual Enhancement Engine
• » Block Diagram
• » What Is a CBB?
• » Platform Features and Benefits
• » Proven System Block Options
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Platform Summary

ArcticLink II is the world’s first ultra-low power, solution platform optimized for Visual Enhancement Engine (VEE™).

QuickLogic has partnered with Apical Limited to bring the patented VEE technology to the mobile world.

VEE technology transforms the mobile multimedia experience by:

• Significantly enhancing image/video quality through dynamic range control
• Allowing viewing image/video quality under low backlight or bright ambient light conditions

The ArcticLink II Solution Platform with integrated VEE technology directly addresses the challenges confronting hand-held mobile multimedia device OEMs and ODMs. As consumers demand a higher quality user experience from mobile devices, OEMs and ODMs must leverage R&D investments and maximize the return on the design effort. With more video content moving to mobile devices, technical challenges for designers become more complex and battery life increasingly a critical factor. The ArcticLink II Solution Platform family is specifically designed to address the issues of battery life and user experience, while providing the flexibility critical to portable and mobile devices.

Visual Enhancement Engine

The ArcticLink II Solution Platform with VEE technology is implemented as a low-power single-chip platform with programmable fabric up to 27 Customizable Building Blocks (CBBs). Seamlessly integrated into the display path, VEE enhances the user’s mobile multimedia visual experience while drastically reducing backlight power to extend battery life.

A significant issue when designing mobile multimedia devices is how to conserve power when playing back video content. A common solution is to lower the backlight level of the LCD display as it consumes 30-50% of the total system power. Unfortunately, doing so dramatically reduces the effective dynamic range of the content being displayed and diminishes the user experience. QuickLogic’s proprietary VEE solution greatly enhances image and video quality by dynamically compressing the display range to match the characteristics of the LCD, resulting in a substantially better viewing experience under low backlight or bright ambient light conditions.

Block Diagram

ArcticLink II Platform Architecture

Platform Features and Benefits

• Integrates leading edge VEE technology
• Supports MIPI DSI with built-in D-PHY; up to WVGA resolution
  • Display standard developed by the MIPI alliance
  • Lower power, lower cost and lower pin count
  • Lower noise and higher reliability going through the hinge of the clamshell, swivel and slider phones
• Increases capacity within the programmable fabric for additional functionality and connectivity solutions
  • Flexible programmable architecture
  • Low power based on QuickLogic’s patented ViaLink® technology
• Small footprint packaging for portable and mobile applications
  • WLCSP: 0.4mm pitch
  • BGA: 6x6mm, 0.5mm pitch

ArcticLink II packages

What is a CBB?

A customizable building block (CBB) is a unit of measurement that represents the on-chip logic that can be used to implement a variety of proven system blocks such as SDIO, PCI, IDE, CE-ATA and NAND Flash controller, to name a few, or custom logic or other system level functions.

Proven System Block Options available for QuickLogic CSSP platforms

Storage
IDE/P-ATA Host Controller supports	All 1” and 1.8” IDE/P-ATA HDDs Data throughput of up to 33 MByte/sec with UDMA Lower processor overhead for ATA timing and polling operation
CE-ATA Host Controller supports	4-bit and 8-bit CE-ATA HDDs CE-ATA 1.1 compliant peripheral interface at speeds up to 52 MHz Hardware implementation for CMD-60 and CMD-61 to lower host processor overhead
NAND Flash Controller supports	Single Level Cell (SLC) NAND flash with 2-bit hardware ECC/EDC Hardware support for wear leveling and bad block management
Secure Digital (SD) Card Host Controller supports	Secure Digital 2.0 standard with support for Secure Digital High Capacity (SDHC) 1-bit and 4-bit operation at speeds of up to 52 MHz
Compact Flash (CF) Host Controller supports	8-bit and 16-bit Compact Flash interface Memory and I/O modes for CF card and peripherals True IDE mode for CF micro hard drives
Multimedia Card (MMC) Controller supports	MMC 4.1 standard for MMC and high capacity SIM card 1-bit, 4-bit, 8-bit operation with speeds up to 52 MHz
Memory Stick (MS) Controller supports	Memory Stick and Memory Stick Pro standards Theoretical maximum data transfer rate of 480 Mbps 4-bit, 8-bit and serial interface widths
Managed NAND Controller with Boot Capability supports	Elimination of the need for NOR Flash in the system Booting from any SD/MMC-based Managed NAND device with support for SDHC devices of 4 GBytes and above SD/MMC controller is SD 2.0 compliant with support for SDHC devices for Managed NAND densities of 4 GBytes and above Supports the latest eMMC standard Supports multiple SD/SDIO/MMC devices or cards on the same bus
Optical Drive Controller (ATAPI) supports	CD and DVD ROM connectivity (ATAPI) Enhanced support for simultaneous DVD ROM and hard disk drives Throughput of greater than 13 MByte/sec Off-loading the application processor from managing the overhead of ATA timing and polling operations
Network
Hi-Speed USB Controller supports	Hi-speed USB 2.0 OTG with integrated high-speed PHY 12-signal ULPI interface available through programmable fabric 8 KByte SRAM on-chip buffer to improve data transfer performance Dedicated DMA controller to off-load CPU from heavy data transfer and manipulation
High-Speed SDIO Controller supports	High-speed SDIO host controller with clock frequency up to 52 MHz Compliance with the latest Secure Digital 2.0 standard SPI, 1-bit and 4-bit modes Rx/Tx FIFOs for higher performance and throughput DMA support for reducing processor bus utilization
MiniPCI for Ethernet, Wi-Fi/WiMAX Controller supports	Leveraging of low-cost PCI-based Wi-Fi modules Up to 264 MByte/sec PCI bus performance, zero wait states Master and target functions for 32-bit data at speeds of 33 and 66 MHz Full compliance to PCI specification 2.3, and Cardbus and Compact PCI compatible
SPI Controller supports	High-speed SPI master controller with clock frequency up to 52 MHz Low cost, low pin count wireless connectivity solution Simple driver architecture customizable to enhance Wi-Fi performance
Bluetooth 2.x + EDR High-Speed UART supports	High-speed UART supporting Bluetooth 2.x with up to 4 Mbit/sec data rate Configurable baud rate customized for different application requirements Configurable flow control and FIFO access
SDIO Client supports	SD v2.0 and SDIO v1.2 compliance with multifunction SDIO support SD 1 bit, SD 4 bit and SPI mode up to 50 MHz Hot insertion/removal, interrupt, Read Wait, Suspend, and Resume CRC7/CRC16
USB Hub supports	Hi-Speed USB upstream port with built-in Hi-Speed USB PHY Each downstream port supporting Full-Speed at 12 MByte/sec and Low-Speed at 1.5 Mbit/sec operation Customizable number of downstream ports Transaction Translator (TT) optimized for maximum bandwidth utilization
Video and Imaging
Visual Enhancement Engine (VEE™) supports	TV-quality visual experience in mobile devices through dynamic range control Greatly enhanced image and video quality even under low backlight or bright ambient conditions Dramatically improved battery life by reducing backlight
MIPI DSI with Built-in D-PHY supports	Display standard develop by the MIPI alliance; up to WVGA resolution Serial interface to reduce pin count, power and cost Lower noise and much improved reliability through hinge of clamshell, swivel and slider phones
X/Y Swap supports	X/Y Swap Operation Frame rate conversion for VGA, NTSC and PAL Power management for stopping all subsystem clocks and shutting down the SDRAM frame buffer Configuration from the host application processor via I2C-compatible bus
High-definition LCD Controller supports	Configurable resolution up to 1024x768 Programmable display aspect ratio Configurable vertical and horizontal scan frequencies Maximum color depth of 24 bits per pixel Embedded SRAM/(Mobile) SDRAM/DDR-SDRAM controller for frame buffer
Intelligence
Direct Memory Access (DMA) supports	Fully customizable DMA controller Lower CPU utilization
Smart Data Transfer (SDT) supports	Onboard intelligence that enables direct port-to-port data transfers, without involving the host CPU bus Significantly improved speed for large file transfer, enhancing user experience and increasing battery life
Data Aggregator (DA) supports	Aggregation of multiple, independent data paths Interface-standard agnostic via multiple proven system blocks and programmable fabric Significantly simplified connections to multiple standard devices via one data pipe to host
Security and Custom Options
Content Protection for Recordable Media (CPRM) supports	C2 cipher algorithm implemented in hardware Working in conjunction with QuickLogic SD/SDIO or P-ATA host controllers Key stored securely in hardware Optimization for SD-Video performance
Serial ID supports	Secure numeric ID, as long as 256 bits can be implemented in the programmable fabric of any PolarPro or ArcticLink Solution Platform Unique number in each CSSP device controlled by a list of desired values provided by OEM/ODM