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Family Summary
The Eclipse family of programmable devices offers a host of system-level features ideal for telecommunications, networking, computing and test applications that require a combination of high performance, high density and embedded RAM.
Block Diagram
Eclipse Device Architecture
Product Features and Benefits
Flexible programmable logic with densities ranging from 250K to 580K system gates
High performance, feature-rich programmable device addresses the density requirements of FPGA and ASIC designers.
Single chip solution
Provides instant-on capability, eliminates the need for external configuration memory and protects intellectual property from design theft and reverse engineering.
Up to 36, 2,304-bit dual-port, high-performance SRAM blocks
Embedded dual-port SRAM and extended I/O support enables integration of several board-level components into a single chip.
Specifications
Embedded dual-port SRAM
- Up to 36, 2,304-bit Dual-port, high-performance SRAM blocks
- Up to 82,900 RAM bits
- RAM/ROM/FIFO Wizard for automatic configuration
- Configurable and cascadable to produce greater memory widths or depths
Programmable I/O
- Supports a wide variety of standards (LVDS, LVPECL, LVTTL, LVCMOS, PCI, GTL+, SSTL2 and SSTL3)
- High-performance, less than 3 ns Tco
- Programmable slew rate control
- Eight independent I/O banks
- Three registers available: input, output and OE
Product Table
| QL6250 | QL6325 | QL6500 | QL6600 | |
| Logic array | 40 x 24 | 48 x 32 | 64 x 48 | 72 x 56 |
| logic cells | 960 | 1,536 | 3,072 | 4,032 |
| RAM modules | 20 | 24 | 32 | 36 |
| PLLs | 4 | 4 | 4 | 4 |
| Distributed clocks | 9 | 9 | 9 | 9 |
| Flip-flops | 2,670 | 3,692 | 7,185 | 9,105 |
| Max gates | 248,160 | 320,640 | 488,064 | 583,008 |
| Max I/Os | 250 | 310 | 347 | 347 |
| Supply voltage | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Package | 208PQFP 280PBGA 484PBGA |
208PQFP 280PBGA 484PBGA |
280PBGA 484PBGA 516PBGA |
280PBGA 484PBGA 516PBGA |
