Eclipse II

Overview

The Eclipse™ II family of programmable devices exceeds the functionality previously addressed by Complex Programmable Logic Devices (CPLDs) and FPGA devices. With an architecture that features high-performance logic, dedicated SRAM blocks and flexible clock architecture, Eclipse II offers FPGA, CPLD and ASIC designers multiple solutions for applications that demand ultra-low power consumption, small form factor packaging, and high design security.

Flexible, feature-rich programmable logic Flexible programmable logic with densities ranging from 47 K to 320 K system gates address the density requirements of CPLD, FPGA and ASIC designers.

Extremely low-power consumption With standby currents as low as 14 µA, the inherent low-power consumption reduces system costs by using smaller, less costly voltage regulators and power sources. Also allows for use in battery-operated systems with strict power budgets.

Full design security Protects intellectual property from design theft and reverse engineering.

High-performance 250 MHz performance with less than 3 ns Tco.

Single chip solution Provides instant-on capability, eliminating the need for external configuration memory.

Up to 24, 2,304-bit Dual-port, high-performance SRAM blocks Embedded Dual-port SRAM and extended I/O support enables integration of several board-level components into a single chip.

Low skew clock networks One dedicated clock network hardwired to all clock inputs. Multiple programmable global clock networks allow bridging to up to 20 clock domains.

User-programmable Phase Locked Loops (PLLs) User-programmable PLLs can be programmed for clock frequency multiplication and division and can be used to improve design I/O timing.

Small form factor packaging Meets the needs of various board-space constrained environments such as PCMCIA, Cardbus, and Mini PCI, with a variety of small outline packages.