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Eclipse

Overview

The Eclipse™ family of programmable devices offers a host of system-level features ideal for telecommunications, networking, computing and test applications that require a combination of high performance, high density and embedded RAM.

Flexible programmable logic with densities ranging from 250K to 580K system gates

High performance, feature-rich programmable device addresses the density requirements of FPGA and ASIC designers.
Single chip solution

Provides instant-on capability, eliminates the need for external configuration memory and protects intellectual property from design theft and reverse engineering.
Up to 36, 2,304-bit dual-port, high-performance SRAM blocks

Embedded dual-port SRAM and extended I/O support enables integration of several board-level components into a single chip.
Embedded dual-port SRAM
  • Up to 36, 2,304-bit Dual-port, high-performance SRAM blocks
  • Up to 82,900 RAM bits
  • RAM/ROM/FIFO Wizard for automatic configuration
  • Configurable and cascadable to produce greater memory widths or depths
Programmable I/O
  • Supports a wide variety of standards (LVDS, LVPECL, LVTTL, LVCMOS, PCI, GTL+, SSTL2 and SSTL3)
  • High-performance, less than 3 ns Tco
  • Programmable slew rate control
  • Eight independent I/O banks
  • Three registers available: input, output and OE