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Family Summary
The Eclipse II family of programmable devices exceeds the functionality previously addressed by Complex Programmable Logic Devices (CPLDs) and FPGA devices. With an architecture that features high-performance logic, dedicated SRAM blocks and flexible clock architecture, Eclipse II offers FPGA, CPLD and ASIC designers multiple solutions for applications that demand ultra-low power consumption, small form factor packaging, and high design security.
Block Diagram
Eclipse II Device Architecture
Product Features and Benefits
Flexible, feature-rich programmable logic
Flexible programmable logic with densities ranging from 47 K to 320 K system gates address the density requirements of CPLD, FPGA and ASIC designers.
Extremely low-power consumption
With standby currents as low as 14 µA, the inherent low-power consumption reduces system costs by using smaller, less costly voltage regulators and power sources. Also allows for use in battery-operated systems with strict power budgets.
Full design security
Protects intellectual property from design theft and reverse engineering.
High-performance
250 MHz performance with less than 3 ns Tco.
Single chip solution
Provides instant-on capability, eliminating the need for external configuration memory.
Up to 24, 2,304-bit Dual-port, high-performance SRAM blocks
Embedded Dual-port SRAM and extended I/O support enables integration of several board-level components into a single chip.
Low skew clock networks
One dedicated clock network hardwired to all clock inputs. Multiple programmable global clock networks allow bridging to up to 20 clock domains.
User-programmable Phase Locked Loops (PLLs)
User-programmable PLLs can be programmed for clock frequency multiplication and division and can be used to improve design I/O timing.
Small form factor packaging
Meets the needs of various board-space constrained environments such as PCMCIA, Cardbus, and Mini PCI, with a variety of small outline packages.
Product Table
| QL8025 | QL8050 | QL8150 | QL8250 | QL8325 | |
| Logic array | 16x8 | 16x16 | 32x32 | 40x24 | 48x32 |
| Logic Cells | 128 | 256 | 640 | 960 | 1,536 |
| RAM modules | 4 | 4 | 16 | 20 | 24 |
| PLLs | 4 | 4 | |||
| Distributed clocks | 5 | 5 | 5 | 9 | 9 |
| Flip-flops | 532 | 884 | 1,709 | 2,670 | 4,002 |
| Max gates | 47,052 | 63,840 | 188,946 | 248,160 | 320,640 |
| Max I/Os | 92 | 124 | 143 | 250 | 310 |
| RAM Bits | 9,216 | 9,216 | 36,864 | 46,100 | 55,300 |
| ECUs | 10 | 12 | |||
| Package (mm) |
100VQFP 196TFBGA 144TQFP |
100VQFP 196TFBGA 101TFBGA(6x6) 144TQFP |
196TFBGA(12x12) 196TFBGA(8x8) 144TQFP 208PQFP |
208PQFP 280LFBGA 484BGA |
208PQFP 280LFBGA 484BGA |
