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Family Summary
The Eclipse Plus family of programmable devices combines high-performance embedded DSP functions with high-speed programmable logic to create a unique system-level solution. Eclipse Plus devices match the integration and performance levels of standard products with the flexibility of programmable logic.
Traditional programmable logic architectures do not implement arithmetic functions efficiently or effectively. These functions require high logic cell usage while garnering only moderate performance results. By embedding the ECUs, the Eclipse Plus family can address various arithmetic functions efficiently and effectively, providing a robust DSP platform. A three-bit instruction set, sequenced from the logic array, memory or external pins, dynamically configures each ECU for any of eight possible operations including: Registered or Flow-Through Multiply, Add, Multiply-Add, or Multiply-Accumulate.
Block Diagram
Eclipse Plus Device Architecture
Product Features and Benefits
Flexible programmable logic with densities ranging from 250 K to 580 K system gates
High performance, feature-rich programmable device addresses the density requirements of FPGA and ASIC designers.
High-performance
250 MHz performance with less than 3 ns Tco.
Single chip solution
Provides instant-on capability, eliminating the need for external configuration memory.
Product Table
| QL7100 | QL7120 | QL7160 | QL7180 | |
| Logic array | 40 x 24 | 48 x 32 | 64 x 48 | 72 x 56 |
| Logic Cells | 960 | 1,536 | 3,072 | 4,032 |
| RAM modules | 20 | 24 | 32 | 36 |
| PLLs | 4 | 4 | 4 | 4 |
| Distributed clocks | 9 | 9 | 9 | 9 |
| Flip-flops | 2,670 | 3,692 | 7,185 | 9,105 |
| Max gates | 292,160 | 373,440 | 558,464 | 662,208 |
| Max I/Os | 250 | 310 | 347 | 347 |
| RAM Bits | 46,100 | 55,300 | 73,700 | 82,900 |
| ECU Total | 10 | 12 | 16 | 18 |
| Package | 208PQFP 280PBGA 484PBGA |
208PQFP 280PBGA 484PBGA |
280PBGA 484PBGA 516PBGA |
280PBGA 484PBGA 516PBGA |
