Platforms » PolarPro & PolarPro II Family

PolarPro® & PolarPro® II Solution Platform

Platform Summary

The award winning PolarPro families of programmable platforms, including PolarPro and PolarPro II, were purposely architected to meet the interconnect and system logic requirements of power sensitive and portable applications. It is based on QuickLogic patented ViaLink® technology to offer programmability with ASIC-like power consumption. The PolarPro family offers a spectrum of platforms with ranging from 8 to 240 Customizable Building Blocks (CBBs), embedded SRAM and advanced clock management. Very Low Power (VLP) mode puts the entire device in sleep mode, drawing as low as 2.2µA, while maintaining I/O status and internal register values.

The PolarPro has won multiple industry awards. Packages as small as 5x5mm BGA package are designed specifically for mobile applications.

What is a CBB?

A customizable building block (CBB) is a unit of measurement that represents the on-chip logic that can be used to implement a variety of proven system blocks such as SDIO, PCI, IDE, CE-ATA and NAND Flash controller, to name a few, or custom logic or other system level functions.

Block Diagrams

PolarPro Platform Architecture

PolarPro Platform Architecture

Platform Features and Benefits

Library of proven system blocks to choose from

Ability to mix and match system blocks allows for high degree of product and/or customer-specific customization

8 ~ 240 Customizable Building Blocks

Range of capacity enables flexibility to tailor CSSP to exact requirements

On-Chip SRAM, FIFO and DMA Controllers

Autonomous data transfers reduce application processor overhead

Proven System Block Options available for QuickLogic CSSP solutions

Proven System Block Options available for QuickLogic CSSP solutions
Please click here for the complete list of Proven System Block options

 

Documentation

Solution Platform Briefs

PolarPro Solution Platforms Brief  908.8KB (5/20/2008)

Solution Guides

QuickLogic Companion Solutions for the Marvell® PXA Application and Communication Processor Families  382.2KB (6/2/2008)

White Papers

Customer Specific Standard Products Ease Mobile Device Design (Rev. E)  985.2KB (4/15/2009)
PolarPro - The Optimal Choice for Low Power Designs (Rev. C)  81.3KB (8/7/2008)
QuickLogic Programmable Logic Power Consumption (Rev. A) PDF 673.7KB (3/15/2007)
X/Y Swap Design for Simultaneous LCD and TV-Out Display in Handheld Electronic Devices (Rev. B) PDF 120.3KB (1/20/2009)

Application Notes

86: QuickLogic PolarPro® RAM and Embedded FIFO Controller (Rev. B) PDF 415.4KB (6/24/2008)
88: Minimizing Energy Consumption with Very Low Power Mode in PolarPro FPGAs (Rev. D) PDF 244.6KB (12/2/2008)

Data Sheets

PolarPro® Device Data Sheet - 86-Pin TFBGA QL1P100 (Rev. E) PDF 1028.2KB (7/10/2008)
PolarPro® Device Data Sheet - QL1P075, QL1P100, QL1P200, and QL1P300 (Rev. D) PDF 1680.7KB (1/21/2009)
PolarPro® Device Data Sheet - QL1P600 and QL1P1000 (Rev. D) PDF 1140.2KB (7/10/2008)
PolarPro® Solution Platform Family Data Sheet (Rev. C) PDF 1257.7KB (1/27/2009)

Reliability Reports

QuickLogic Reliability Report 2008 (Rev. A) PDF 115KB (3/26/2008)

Mechanical Drawings

PF144 - TQFP, 20x20x1.4mm, 1.00/0.10mm Form (Rev. C) PDF 62.6KB (2/27/1992)
PS256 - LBGA, 17x17x1.4mm, 2L, PS256 Ball, 1.00mm Pitch (Rev. A) PDF 74.2KB (8/29/2005)
PS324 - LBGA, 19x19x1.38mm, 4L, PS324 Ball, 1.00mm Pitch (Rev. A) PDF 79.6KB (5/3/2007)
PT196 - TFPBGA, 12x12x1.20mm, 2L, 196 Ball, 0.80mm Pitch (Rev. A) PDF 65.3KB (5/14/2003)
PU101 - TFBGA, 6x6x1.2mm, 2L, PU101 Ball, 0.50mm Pitch (Rev. B) PDF 71.8KB (10/14/2006)
PU121 - TFBGA, 6x6x1.20mm, 2l, PU121 Ball, 0.50mm Pitch (Rev. C) PDF 58.5KB (1/23/2008)
PU132 - TFBGA, 8x8x1.20mm, 2L, PU132 Ball, 0.50mm Pitch (Rev. C) PDF 77.1KB (10/12/2006)

Errata Sheets

PolarPro® Errata (Rev.D) PDF 71.2KB (11/3/2008)

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