What’s on this page?
Related information
Contact Us
If you have questions for our programmable device expert, please contact us.
End-of-Life Annoucement
End-of-Life has been announced for the pASIC 3 PLCC packages. Please click here for more details.
Family Summary
QuickLogic’s pASIC 3 family of programmable devices range from 5,000 to 75,000 system gates. Members of the pASIC 3 Family feature 3.3 V operation with 5.0 V I/O compatibility, and are available in commercial, industrial and military temperature grades.
Block Diagram
pASIC 3 Device Architecture
Product Features and Benefits
High-performance and high-density
- Densities up to 75,000 system gates with up to 316 I/Os
Advanced I/O capabilities
- Multi-volt compatible I/Os for 3.3 V and 5.0 V system interfaces
- PCI compatibility with 3.3 V and 5.0 V buses
- Full JTAG boundary scan
- Registered I/O cells with individually controlled clocks and output enables
Easy to use / fast development cycles
- Abundant interconnect makes devices 100% routable with pin-outs locked
- Variable-grain logic cell provides high-performance and 100% logic utilization
- Comprehensive design tools include fast, efficient Verilog/VHDL synthesis
Product Table
| QL3004 | QL3004E | QL3006 | QL3012 | QL3025 | QL3040 | QL3060 | |
| Logic Cells | 96 | 96 | 160 | 320 | 672 | 1,008 | 1,584 |
| Distributed clocks | 6 | 4 | 4 | 4 | 4 | 8 | 8 |
| Flip-flops | 178 | 178 | 322 | 438 | 876 | 1,260 | 1,900 |
| Max gates | 5,188 | 5,188 | 8,008 | 15,740 | 32,616 | 48,384 | 75,232 |
| Max I/Os | 82 | 82 | 82 | 118 | 204 | 252 | 316 |
| Package | 100TQFP | 100TQFP | 100TQFP | 100TQFP 144TQFP |
144TQFP 208PQFP 256PBGA |
208PQFP 456PBGA |
208PQFP 456PBGA |
