QuickWorks

1. My Verilog design works in behavioral simulation, but I can't get it to run at speed. What should I do?

A. Good coding techniques are essential. First look at the design and find out if you have used nested if/else statements.

An example of this is:

if (a = 8'h0)
x = state1;
else if (a = 8'h2)
x = state2;
else if (a= 8'hF)
x = state3;

etc .....

The above would create priority decoders, which in turn would cause the last statement to have a terrible amount of delay. This can be avoided by using the case statement, allowing parallel decoding of the above logic. Second, try pipelining the design. This technique breaks up the logic into distinct smaller pieces. For instance, instead of trying to multiply, and then adding different resultants, try registering the multiplier output. Then take the registered multiplier output and run this through the adder, and registering the adder output. Look below for an example:

before:
always @(posedge clock)
begin
x = (a * b) + (c * d);
end

after :
always @(posedge clock)
begin
x_set1 = (a * b);
x_set2 = (c * d);
end

always @(posedge clock)
begin
x = x_set1 + x_set2;
end

The above technique will use more flip flops, but will increase the overall frequency.

2. Why can't I fix the pin assignments for some of the pins in my HDL design?

A. When doing HDL designs, fixing pin locations is done through the "ql_placement" command in the *.sc file.

During the synthesis stage, Synplify-Lite determines what type of pad is most suitable for a signal. Since each pin (I/O, ACLK/I or GCLK/I) can only be connected to certain types of pads (I/O pins to I/O pads, ACLK/I and GCLK/I pins to clock or high-drive pads), there might be a problem.

A regular I/O signal may end up being attached to a clock pad or a clock signal being connected to an I/O pad. The way to solve this is to specify the pad type as well as its placement for each signal using the "pad_type" command. This will force Synplify-Lite to use the correct pad type.

Also notice that in the .sc file, the signal is case-sensitive. For more information, please refer to the QuickNote titled "Fixing I/Os in Synplify-Lite"

3. When creating a Verilog or VHDL file from a .rom file, why does the RAM/ROM/FIFO Wizard give a syntax error?

A. This could be due to the format of the .rom file. Shown below is the correct format of the .rom file. The words in parenthesis are not to be included (they are only included as explanation): rom = (the file name of the design) depth = (the depth of the ROM)
width = (the width of the ROM)
asyncread = (put true or false depending on what you need)
radix = (can be hex or binary)

data
[0] = "00"
[1] = "01"
[2] = "ff"
[3] = "00"
[4] = "22"
[5] = "33"
[6] = "44"

[7] = "55"
[8] = "a3"
[9] = "00"
[10] = "45"
[11] = "88"
[12] = "99"
[13] = "10"
etc.

Notice that the addresses of the ROM are enclosed in brackets, and NOT written in hexadecimal form. This is the most common error made. Make sure you write the addresses of the ROM in decimal form.

4. The Message, "VHDL compiler exit on status xxxxxxx" appeared during source files compilation under Synplify-Lite. How can I find out the problem with the source code?

A. Open the .tlg file under your design directory using Turbo Writer. The contents of the .tlg file will typically show whether the error is due to unusual coding in the source files. Making slight changes to the source files accordingly should resolve the complier problem.

5. Sometimes, Synplify-Lite reports a mapper failure. The error is not very helpful, since it only says, "Mapper Fails." Is there a "next step" after encountering this error?

A. Go to the Log file, and scroll to the bottom for a line that says: "Mapper failure due to driver errors." Approximately three to four lines higher, the signal name, and sometimes the type of driver error (multiple drivers, missing driver, mixed driver types, etc.) will be reported. The best way to troubleshoot this problem is to follow the signal throughout the design. But, the first thing to keep in mind is that QuickLogic devices do not support internal tri-states. Often this error is due to the use of internal tri-states.
Below is an example that would cause a driver error:

output A1;
signal A2, B;
A1 <= B;
pad instantiation (In <= A2,
Out <= A1);

This would fail because A1 has multiple drivers: the signal B, and the output of the pad. The mistake occurs because B has been assigned to A1. B should have been assigned to A2 (which is the input of the pad).

6. What is the input hysteresis on pASIC 3, QuickRAM and QuickPCI families?

A. The pASIC 3, QuickRAM and QuickPCI families all have roughly 40 mV of hysteresis on the inputs.

7. What is the QuickLogic-recommended rinsing solution for devices?

A. Hot DI water as the final rinse is our recommendation. Pre-rinse would depend on the type of flux used in the reflow solder process or the solder paste formulation used by the assembly vendor.

8. How can I contact your sales department?

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