The Jupiter application reference design provides a vehicle to explore the full capabilities of the ArcticLink II CX solution platform.
The first goal is to characterize the performance of the ArcticLink II CX solution platform. To accomplish this, the Jupiter application reference design provides a USB Controller with PHY as its gateway into transferring data on two independent SDXC channels. Each channel supports a range of memory formats. These include full-sized SD cards (in data widths up to 4-bits), removable eMMC cards (in data widths up to 8-bits), and embedded eMMC devices (in data widths up to 8-bits). These channels can be used individually to measure the performance per channel, or can be combined to form an interleaved storage system for even greater performance. In addition, an AES Proven System Block (PSB) in the ArcticLink II CX provides hardware-based encryption to speed the transfer of data during secure data storage applications. This provides a way to offer high data security without sacrificing data storage performance.
The second goal is to provide a reference design to the system designer. Fundamentally, a reference design should show the practical considerations when creating a product. The reference design platform does this on several levels when creating a product with the ArcticLink II CX solution platform. Primarily, it is to show the expected connections to its standard interfaces. These interfaces include a USB Controller with PHY, twin mass storage channels, and GPIO from the fabric-based PSBs. Additionally, it shows QuickLogic’s recommended platform design guidelines. Principal amongst these are examples of how to achieve low power, low noise, and improved signal integrity.
The low power design methodology applied to the reference design consists of two parts. The first is the ability to disconnect power to all mass storage devices. Consequently, leakage current during power up and suspend modes are eliminated. Secondly, the ArcticLink II CX solution platform provides an internal, low frequency clock that allows the platform level oscillator to be disabled and placed into a low power mode. By doing so, the absolute minimum of power consumption can be achieved during USB suspend modes.
To achieve low noise, the reference design implements filters on all devices that can be a significant source of noise within the platform. This filtering provides a way to prevent components such as on-platform Phase- Locked Loops (PLLs) from generating noise into the platform, and also prevents platform level noise from causing instability within these PLLs.
The third goal is to achieve good signal integrity. The reference platform design utilizes a PCB stackup and trace routing rules that reduce impedance discontinuities and crosstalk. These can be sources of poor signal integrity, resulting in unreliable operation and excessive electromagnetic interference (EMI). By achieving good signal integrity, operations such as USB transfers have greater operational margins in a wider variety of end-user environments. Similarly, reduced EMI helps avoid interference with nearby devices, as well as to quickly achieve the required regulatory approvals.
The expansion board connector supports expansion boards that can be customized to the requirements of the development project. For example, this board can be used to host a simple set of headers for diagnostic tracing with a logic analyzer or oscilloscope. Alternatively, the expansion board design can host multiple downstream USB ports via the Jupiter application reference platform dual ULPI busses.
By meeting these three basic goals, the form-factor board provides the ability to demonstrate the value of the Jupiter application reference design.