Aurora™ Place & Route Tools and Borealis™ eFPGA Compiler

Comprehensive Software Tools
for easy eFPGA integration

Aurora™ Place & Route Tools – FPGA Design

Customers who are interested in integrating eFPGA in their next SoC or ASIC design can now use Aurora to design and configure the eFPGA.

  • FPGA standard flow
  • Synthesis: Mentor Graphics Precision
  • Simulation: Compatible with industry standard EDA simulators
    • NC-Sim, VCS, Questa, ModelSim
  • Dynamic FPGA size estimation and device configurator
  • Back annotated timing data for performance analysis
  • Power calculator
  • TCL command line standard flow support

 

Borealis™ eFPGA Compiler – SoC Integration

Once the size of eFPGA has been determined and configured using Aurora, customers can easily generate all the necessary netlists for final SoC/ASIC integration.

  • Netlist file – CDL & .v file
  • ASIC .lib file
  • LEF file
  • Final .GDS file

 

Aurora Block Diagram

eFPGA Software Design Flow

 

Screen Shot

Aurora eFPGA Design Tool Screenshot

Documentation

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