QuickLogic provides a complete design environment for Field Programmable Gate Array (FPGA) designs. QuickLogic development software helps you increase productivity, shorten design cycles, achieve design performance and power requirements quickly and efficiently. QuickLogic provides tools to guide you from concept to silicon.

QuickWorks® supports Windows operating systems, and provides a comprehensive design environment ranging from schematic and HDL-base design entry, HDL language editors and tutorials, logic synthesis, place and route, timing analysis, and simulation support. QuickLogic has partnered with Mentor Graphics and Aldec Inc. to provide industry leading synthesis and simulation tools, as well as provide an interface to other industry standard EDA tools.

In addition, QuickLogic provides various reference design kits and software development kits to shorten your verification cycles.

QuickWorks Flow
Design Flow

QuickWorks Synthesis

Part Number Included Software
  • Schematic Capture
  • Place & Route
  • Mentor Graphics Precision Synthesis

Frequently Asked Questions

Good coding techniques are essential. First look at the design and find out if you have used nested if/else statements.

An example of this is:

if (a = 8'h0)
x = state1;
else if (a = 8'h2)
x = state2;
else if (a= 8'hF)
x = state3;

etc .....

The above would create priority decoders, which in turn would cause the last statement to have a terrible amount of delay. This can be avoided by using the case statement, allowing parallel decoding of the above logic. Second, try pipelining the design. This technique breaks up the logic into distinct smaller pieces. For instance, instead of trying to multiply, and then adding different resultants, try registering the multiplier output. Then take the registered multiplier output and run this through the adder, and registering the adder output. Look below for an example:

always @(posedge clock)
x = (a * b) + (c * d);
always @(posedge clock)
x_set1 = (a * b);
x_set2 = (c * d);
always @(posedge clock)
x = x_set1 + x_set2;

The above technique will use more flip flops, but will increase the overall frequency.

When doing HDL designs, fixing pin locations is done through the "ql_placement" command in the *.sc file.

During the synthesis stage, Synplify-Lite determines what type of pad is most suitable for a signal. Since each pin (I/O, ACLK/I or GCLK/I) can only be connected to certain types of pads (I/O pins to I/O pads, ACLK/I and GCLK/I pins to clock or high-drive pads), there might be a problem.

A regular I/O signal may end up being attached to a clock pad or a clock signal being connected to an I/O pad. The way to solve this is to specify the pad type as well as its placement for each signal using the "pad_type" command. This will force Synplify-Lite to use the correct pad type.

Also notice that in the .sc file, the signal is case-sensitive. For more information, please refer to the QuickNote titled "Fixing I/Os in Synplify-Lite"

This could be due to the format of the .rom file. Shown below is the correct format of the .rom file. The words in parenthesis are not to be included (they are only included as explanation): rom = (the file name of the design) depth = (the depth of the ROM) width = (the width of the ROM) asyncread = (put true or false depending on what you need) radix = (can be hex or binary)

[0] = "00"
[1] = "01"
[2] = "ff"
[3] = "00"
[4] = "22"
[5] = "33"
[6] = "44"

[7] = "55"
[8] = "a3"
[9] = "00"
[10] = "45"
[11] = "88"
[12] = "99"
[13] = "10"


Notice that the addresses of the ROM are enclosed in brackets, and NOT written in hexadecimal form. This is the most common error made. Make sure you write the addresses of the ROM in decimal form.

Open the .tlg file under your design directory using Turbo Writer. The contents of the .tlg file will typically show whether the error is due to unusual coding in the source files. Making slight changes to the source files accordingly should resolve the complier problem.

Go to the Log file, and scroll to the bottom for a line that says: "Mapper failure due to driver errors." Approximately three to four lines higher, the signal name, and sometimes the type of driver error (multiple drivers, missing driver, mixed driver types, etc.) will be reported. The best way to troubleshoot this problem is to follow the signal throughout the design. But, the first thing to keep in mind is that QuickLogic devices do not support internal tri-states. Often this error is due to the use of internal tri-states.

Below is an example that would cause a driver error:

output A1;
signal A2, B;
A1 <= B;
pad instantiation (In <= A2,
Out <= A1);

This would fail because A1 has multiple drivers: the signal B, and the output of the pad. The mistake occurs because B has been assigned to A1. B should have been assigned to A2 (which is the input of the pad).

The pASIC 3, QuickRAM and QuickPCI families all have roughly 40 mV of hysteresis on the inputs.

Hot DI water as the final rinse is our recommendation. Pre-rinse would depend on the type of flux used in the reflow solder process or the solder paste formulation used by the assembly vendor.

Please find the sales office locations near you.

Software Download

Please read the software license agreement.

Name Version Size Updated Notes

QuickWorks 2010.4.1

2010.4.1 207 MB January 19, 2011

This version doesn't include Mentor Graphics Precision Synthesis. Please download Mentor Graphics Precision Synthesis and Synthesis Library separately.

QuickWorks 2010.3.1.1 Patch

2010.3.1.1 13.4 MB October 4, 2010

This patch is applicable only on QuickWorks2010.3.1 Release build.

QuickWorks 9.7.4

license.dat for v9.7.4 (Right click the link to save the file)

9.7.4 301.4 MB February 5, 2008

For EOL devices. Please make sure you don't have any other QuickWorks versions installed on your system.

License installation instructions:Please copy the license.date license file to the data directory of your SpDE installation. The default installation directory path is C:\pasic\spde\data\license.dat.

QL9600 Software

1.35a 4.9 MB June 9, 2015

QL9600 Software for System General Programmers


9.4.1 RC3 64 MB  

IBIS Model Visual Editor/Viewer

      Download  from www.mentor.com

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