Pin Constraint Manager GUI

User can easily assign and place I/O interfaces using an intuitive Graphical User Interface

Improved Carry Chain Architecture

Enhanced carry chain architecture improves performance by as much as 20%

Asymmetric BlockRAM (BRAM) Inferencing

Aurora’s Inferencing feature streamlines the implementation of reconfigurable computing algorithms, by automatically adapting BlockRAM (BRAM) read/write widths, eliminating the need for manual RTL design modifications.

State-of-the-Art “Single Stage” Routing

The Single Stage Routing algorithm significantly enhances the maximum operating frequency (Fmax) of designs for QuickLogic eFPGA cores. It has shown an impressive Fmax increase of up to 24% in QuickLogic’s benchmark designs, ultimately optimizing FPGA performance.

Power Calculation

The power calculator in the Aurora FPGA Tools calculates dynamic power from a user’s design’s clock frequencies and extracted capacitance models extracted from QuickLogic’s ASIC-like design methodology.

The Tools simplify power calculation for eFPGA cores by automatically estimating dynamic power consumption based on design clock frequencies and capacitance models. This automation, coupled with QuickLogic’s CI infrastructure and CLI options, enables users to efficiently calculate power consumption across a range of designs.

Support for Windows and Linux OS Platforms

Aurora is now available on Windows 11/Windows 10 OS platform and all of the major Linux distributions (including Centos, RedHat, and Ubuntu), via a unified Linux installation package.

Interactive Path Analysis (IPA) Feature

A standout addition is the Interactive Path Analysis (IPA) within the new Graphical User Interface (GUI). Interactive Path Analysis (IPA) Feature allows users to debug their design timing in lot more detail by highlighting the routing for critical paths in the design. This will enable users to decide how they can improve the design’s timing performance. The inclusion of IPA exemplifies Aurora’s evolution towards more intuitive and insightful design analysis, facilitating smoother development processes for engineers.

Usability Features

The tools includes several developments to the workflow to improve overall user’s design time. These include:

• Upgraded Integrated Development Environment view screenshot
• Project Workspace view screenshot
• Execution Control Panel view screenshot
• Expanded Log Console view screenshot
• Physical Viewer view screenshot
• Critical Path Analysis view screenshot
• Detailed Timing/Utilization Information view screenshot