Logic that's fused in silicon, not loaded from memory.
Immutable. Fixed. Field-proven.
Antifuse FPGAs
One-time-programmable ViaLink® FPGAs for instant-on, mission-critical, low-power designs — trusted across three decades and more than 50 million shipped devices.
- Zero boot-up time
- Non-volatile / no bitstream to load
- 3.3 V drive / 5 V-tolerant I/O on pASIC 3 & QuickRAM
- Deployment heritage
- Fixed-in-structure logic for fuze & S&A safety features
Fuze & Safe-and-Arm Devices
Safety logic must remain fixed and protected from unintended alteration. Antifuse makes that inherent in the configuration technology.
- Regulatory Compliance: MIL-STD-1316F mandates that fuzing safety logic remain immutable against environmental alteration, with logic devices evaluated per JOTP-051.
- The Antifuse Advantage: QuickLogic's OTP antifuse fabric uses permanent physical interconnects rather than rewritable charge-based memory, delivering a naturally fixed-in-structure implementation.
- Streamlined Validation: Because the configuration is permanent, JOTP-051 rules requiring pre-execution integrity checks (like CRC verification) on charge-based memory do not apply to the antifuse fabric itself. Standard safety analysis and Service Safety Authority approval still apply.
Standards referenced
MIL-STD-1316F
Fuze design safety criteria. Safety-related logic must be protected from erasure, alteration, or reconfiguration by credible environments the system would otherwise survive.
JOTP-051
DoD Technical Manual for the Use of Logic Devices in Safety Features. Sets validation requirements for logic devices in safety functions, including CRC-based integrity checks when charge-based memory implements a safety feature.
Built for long lifecycles. QuickLogic's antifuse process nodes (0.18µm–0.35µm) have been in continuous production for decades, giving these families a proven track record of long-term availability and reliability — a real advantage for programs that need consistent supply over a long service life. See each family below for current new-design guidance, or contact sales@quicklogic.com. to confirm production status and lead times for a specific device.
Why antifuse
The programming element is a physical connection created at the QuickLogic Programming Center or at the engineer's desk — not in-system on a fielded board. There's no configuration SRAM to load, and no external configuration bitstream or configuration memory to extract. For legacy-system interfacing, pASIC 3 and QuickRAM provide 3.3 V output drive with 5 V-tolerant inputs.
Security by construction
Configuration is physically fused into silicon rather than loaded from external memory. There is no conventional configuration memory or external configuration bitstream to read out, substantially reducing the configuration-related attack surface associated with loadable devices.
Instant-on
Zero boot-up time makes these a fit for time-sensitive communications and munitions projects where an SRAM FPGA's load delay isn't acceptable, and where the FPGA must boot up predictably the same way every time.
Advanced clocking
Multiple global and local clock networks, with configurable clock management on supported families.
Optional embedded memory
Some families include dual-port embedded SRAM and dedicated FIFO controllers on-chip.
Low power
Antifuse configuration consumes no configuration-memory refresh power, enabling very low standby power.
Small footprint
ViaLink technology enables compact implementations for many applications.
What it means for your program
Simplified supply chain
Secure Factory Programming available with unique part number.
Cost-effective
No separate configuration memory chip — minimizes BOM, PCB area, and total cost.
Easier certification
The absence of external configuration memory can simplify portions of system safety and security analysis.
Fast time-to-market
Prototype at your desk; production lead times are short relative to custom ASIC flows.
Better battery life
Very low standby power can extend battery life and reduce thermal load.
Field-proven
Three decades of deployment heritage across defense, aerospace, industrial, and mission-critical applications.
ViaLink® antifuse cross-section
How it works: ViaLink® technology
Each programmable connection point starts as a high-impedance via between two metal layers. Applying the programming voltage creates a permanent, low-resistance conductive path across that via — the inverse of a conventional fuse, and the origin of the "antifuse" name.
Because the link is a physical metal connection rather than a value stored in rewritable configuration memory, it is not erased or reloaded during normal operation. There is no conventional configuration memory or external configuration bitstream to read out, supporting the security and instant-on characteristics above.
Which family fits your design?
A quick comparison across the recommended antifuse families, from smallest footprint to highest gate count. See each family's spec table for exact part-level guidance. Legacy families are listed separately below.
| Family | Logic cells | Process | I/O voltage support | Status | Best fit when you need… | |
|---|---|---|---|---|---|---|
| Drive | Tolerance | |||||
| pASIC 3 | 96 – 1,584 | 0.35µm, 4-layer | 3.3 V | 3.3 / 5 V | 6 of 7 Devices Recommended | The lowest-cost entry point with the widest package selection |
| QuickRAM | 160 – 1,584 | 0.35µm, 4-layer | 3.3 V | 3.3 / 5 V | Recommended | pASIC 3 array sizes plus dedicated block RAM |
| Eclipse | 960 – 4,032 | 0.25µm, 5-layer | 2.5 / 3.3 V | 2.5 / 3.3 V | 4 Recommended | The Eclipse Plus array sizes without the DSP-oriented ECUs |
| Eclipse Plus | 960 – 4,032 | 0.18µm, 6-layer | 2.5 / 3.3 V | 2.5 / 3.3 V | 3 of 4 Recommended | DSP-heavy signal processing, larger ECU counts, and PLLs |
I/O voltage support is family-dependent. pASIC 3 and QuickRAM provide 3.3 V drive and 5 V input tolerance; consult the applicable device datasheet for supported standards, bank configuration, and operating conditions.
“Mixed” families remain on this page in full; only the devices marked Legacy in each spec table are not recommended for new designs. Recommended and Legacy designations reflect current QuickLogic product-management guidance; confirm status and availability prior to design-in.
Product families
Full specifications for every antifuse line.
pASIC 3 — Lowest cost entry 6 of 7 Devices Recommended
pASIC 3 Family Data Sheet (PDF)
| Feature | QL3004 | QL3004E Legacy | QL3006 | QL3012 | QL3025 | QL3040 | QL3060 |
|---|---|---|---|---|---|---|---|
| Max gates | 5,188 | 5,188 | 8,008 | 15,740 | 32,616 | 48,384 | 75,232 |
| Logic array | 8×12 | 8×12 | 10×16 | 20×16 | 28×24 | 36×28 | 44×36 |
| Logic cells | 96 | 96 | 160 | 320 | 672 | 1,008 | 1,584 |
| Max flip-flops | 178 | 178 | 322 | 438 | 876 | 1,260 | 1,900 |
| Max I/O | 74 | 74 | 74 | 110 | 196 | 244 | 308 |
| Package — TQFP 100 | 100 | 100 | 100 | 100 | 100 | – | – |
| Package — TQFP 144 | – | – | – | 144 | 144 | – | – |
| Package — PQFP 208* | – | – | – | – | 208 | 208 | 208 |
| Package — PBGA 256 | – | – | – | – | 256 | – | – |
| Package — PBGA 456 | – | – | – | – | – | 456 | 456 |
* 208-pin PQFP package is not recommended for new designs.
QuickRAM — Block RAM on-chip Recommended for new designs
QuickRAM Family Data Sheet (PDF)
| Feature | QL4009 | QL4016 | QL4036 | QL4058 | QL4090 |
|---|---|---|---|---|---|
| Max gates | 44,964 | 61,820 | 97,128 | 131,328 | 176,608 |
| Logic array | 16×16 | 20×16 | 28×24 | 36×28 | 44×36 |
| Logic cells | 160 | 320 | 672 | 1,008 | 1,584 |
| Max flip-flops | 242 | 438 | 876 | 1,260 | 1,900 |
| Max I/O | 74 | 110 | 196 | 244 | 308 |
| RAM modules | 8 | 10 | 14 | 18 | 22 |
| RAM bits | 9,216 | 11,520 | 16,128 | 20,736 | 25,344 |
| Max I/O — QFN 56 NEW PACKAGE! | 32† | 32 | – | – | – |
| Max I/O — TQFP 100 | 74 | 74 | – | – | – |
| Max I/O — TQFP 144 | – | 110 | 110 | – | – |
| Max I/O — PQFP 208* | – | – | 166 | 166 | 166 |
| Max I/O — PBGA 256 | – | – | 196 | – | – |
| Max I/O — PBGA 456 | – | – | – | 244 | 308 |
* 208-pin PQFP package is not recommended for new designs.
Eclipse — 0.25µm Recommended for new designs
Eclipse Family Data Sheet (PDF)
| Feature | QL6250 | QL6325 | QL6500 | QL6600 |
|---|---|---|---|---|
| Max gates | 248,160 | 320,640 | 488,064 | 583,008 |
| Logic array | 40×24 | 48×32 | 64×48 | 72×56 |
| Logic cells | 960 | 1,536 | 3,072 | 4,032 |
| Max flip-flops | 2,670 | 4,002 | 7,185 | 9,105 |
| Max I/O | 250 | 310 | 347 | 347 |
| RAM modules | 20 | 24 | 32 | 36 |
| RAM bits | 46,100 | 55,300 | 73,700 | 82,900 |
| Package — PQFP * | – | 208 | – | – |
| Package — FPBGA (1.0 mm) | 484 | 484 | 484 | 484 |
| Package — LFBGA (0.8 mm) ** | – | 280 | 280 | 280 |
* 208-pin PQFP and 280-pin LFBGA packages are not recommended for new designs.
Eclipse Plus — DSP / ECU-heavy Recommended for new designs
The same fabric and array sizes as Eclipse, plus Embedded Computational Units (ECUs) — DSP blocks that speed up signal-processing tasks.
Eclipse Plus Family Data Sheet (PDF)
| Feature | QL7100 | QL7120 | QL7160 | QL7180 |
|---|---|---|---|---|
| Max gates | 292,160 | 373,440 | 558,464 | 662,208 |
| Logic array | 40×24 | 48×32 | 64×48 | 72×56 |
| Logic cells | 960 | 1,536 | 3,072 | 4,032 |
| Max flip-flops | 2,670 | 3,692 | 7,185 | 9,105 |
| Max I/O | 250 | 310 | 347 | 347 |
| RAM modules | 20 | 24 | 32 | 36 |
| RAM bits | 46,100 | 55,300 | 73,700 | 82,900 |
| PLLs | 4 | 4 | 4 | 4 |
| ECUs | 10 | 12 | 16 | 18 |
| Package — PQFP (0.5 mm) * | 208 | 208 | – | – |
| Package — LFBGA (0.8 mm) * | 280 | 280 | 280 | 280 |
| Package — PBGA (1.0 mm) * | 484 | 484 | 484 | 484 |
* 208-pin PQFP and 280-pin LFBGA packages are not recommended for new designs.
Eclipse II — Optional ECUs Legacy QL8050 Available
Eclipse II Family Data Sheet (PDF)
| Feature | QL8025Legacy | QL8050(confirm with QuickLogic) | QL8150Legacy | QL8250Legacy | QL8325Legacy |
|---|---|---|---|---|---|
| Max gates | 47,052 | 63,840 | 188,946 | 248,160 | 320,640 |
| Logic array | 16×8 | 16×16 | 32×20 | 40×24 | 48×32 |
| Logic cells | 128 | 256 | 640 | 960 | 1,536 |
| Max flip-flops | 532 | 884 | 1,709 | 2,670 | 4,002 |
| Max I/O | 92 | 124 | 165 | 250 | 310 |
| RAM modules | 4 | 4 | 16 | 20 | 24 |
| RAM bits | 9,216 | 9,216 | 36,864 | 46,100 | 55,300 |
| PLLs | – | – | – | 4 | 4 |
| ECUs | – | – | – | 10 | 12 |
| Package — VQFP | 100 | 100 | – | – | – |
| Package — TQFP | 144 | 144 | 144 | – | – |
| Package — PQFP | – | – | 208 | 208 | 208 |
| Package — LFBGA (0.8 mm) | – | – | 280 | 280 | 280 |
| Package — PBGA (1.0 mm) | – | – | – | 484 | 484 |
Legacy families
These families are not available for new designs. Existing customers should contact sales@quicklogic.com to confirm availability and lead times before design-in.
| Family | Logic cells | Process | I/O voltage | Status | Notes |
|---|---|---|---|---|---|
| PolarPro | 512 – 7,680 | 0.18µm, 6-layer | 1.8 / 2.5 / 3.3 V | Legacy | limited inventory — contact sales@quicklogic.com |
| PolarPro II | 864 | 0.18µm, 6-layer | 1.8 / 2.5 / 3.3 V | Legacy | limited inventory — contact sales@quicklogic.com |
| Eclipse II | 128 – 1,536 | 0.18µm, 6-layer | 1.8 / 2.5 / 3.3 V | Legacy | QL8050 available — confirm with sales@quicklogic.com |
| All other devices contact sales@quicklogic.com | |||||
PolarPro Not recommended for new designs
PolarPro Family Data Sheet (PDF)
| Feature | QL1P075 | QL1P100 | QL1P200 | QL1P300 | QLP600 | QLP1000 |
|---|---|---|---|---|---|---|
| Max gates | 75,000 | 100,000 | 200,000 | 300,000 | 600,000 | 1,000,000 |
| Logic cells | 512 | 640 | 1,536 | 1,920 | 4,224 | 7,680 |
| Max I/O | 168 | 184 | 238 | 238 | 232 | 244 |
| RAM modules | 8 | 8 | 12 | 12 | 24 | 24 |
| FIFO controllers | 8 | 8 | 12 | 12 | 24 | 24 |
| RAM bits | 36,864 | 36,864 | 55,296 | 55,296 | 221,184 | 221,184 |
| CCM(s) | 2¹ | 2¹ | 2 | 2¹ | 2 | 2 |
| Package — WLCSP (0.5 mm) | 99 | – | – | – | – | – |
| Package — TFBGA (0.5 mm), 121 | – | 121 | – | – | – | – |
| Package — TFBGA (0.5 mm), 132 | 132 | 132 | 132 | 132 | – | – |
| Package — TQFP (0.5 mm) | 144 | 144 | – | – | – | – |
| Package — TFBGA (0.8 mm) | 196 | 196 | – | – | – | – |
| Package — LBGA (1.0 mm) | 256 | 256 | 256 / 324 | 256 / 324 | 324 | 324 |
¹ See datasheet for CCM configuration notes on marked devices.
PolarPro II Not recommended for new designs
A single 864 logic-cell part available in three narrow-pitch packages, optimized for low-power, small-footprint applications and manufactured in a 0.18µm, six-layer metal CMOS process.
PolarPro II Family Data Sheet (PDF)
| Feature | QL2P150 |
|---|---|
| Max gates | 150,000 |
| Logic cells | 864 |
| RAM modules | 8 |
| FIFO controllers | 8 |
| RAM bits | 27,648 |
| CCMs | 1 |
| Max I/O — 144 VFBGA (0.4 mm pitch) | 103 |
| Max I/O — 121 TFBGA (0.5 mm pitch) | 81 |
| Max I/O — 64 WLCSP (0.4 mm pitch) | 41 |
© 2026 QuickLogic Corporation. Specifications reformatted for clarity — verify against linked datasheets before finalizing a design.
