In July of this year, we announced that QuickLogic would become the first programmable logic vendor to fully embrace an open source development environment. Specifically, we worked with Antmicro to create a fully open-source suite of tools for our QuickFeather development kit, which features our EOS S3 FPGA SoC platform with an embedded Arm® processor.
The environment we created included SymbiFlow for FPGA development, Renode for SoC Emulation, and Zephyr for RTOS support. We felt that the combination of open-source tools and our QuickFeather kit could be useful for a wide variety of applications, but FPGA-enhanced Machine Learning (ML) was one set of applications we had in mind and TinyML was a particular target.
Now QuickLogic and Antmicro are taking another step forward by collaborating on a joint project with Google. The new project involves the development of Renode simulation and open-source FPGA tooling support for OpenHW Group’s Core-V MCU project featuring the CV32E40P RISC-V core alongside QuickLogic’s eFPGA fabric.
This new platform will build on the open-source RISC-V ISA and complement it with an open-source embedded FPGA to create a powerful, highly integrated, extremely flexible, and ultra-low power target for TinyML applications.
By building on the open-source RISC-V ISA and with an open-source FPGA inside, it will be an extremely capable and flexible target for TinyML applications. This new platform can be evaluated in a pre-silicon form via support from Renode which also includes FPGA co-simulation capability.
We recently joined a keynote panel discussion at the RISC-V Summit, moderated by Michael Gielda of Antmicro, to discuss this collaborative effort along with other TinyML advances. Joining us were Tim Ansell from Google and Zephyr’s Kate Stewart.