As organizations prepare for the transition to post-quantum cryptography (PQC), SoC designers face a significant challenge: how to build hardware that can evolve as cryptographic standards and threats continue to change.
Traditional cryptographic engines are implemented in fixed silicon. While they deliver excellent performance, updating them typically requires an expensive silicon redesign. As NIST continues to drive the industry’s migration toward post-quantum standards, hardware designers need a more flexible approach.
QuickLogic and PQSecure Technologies recently collaborated to demonstrate that post-quantum cryptographic IP can be implemented as a reprogrammable function within an SoC using QuickLogic’s eFPGA Hard IP.
The collaboration successfully implemented PQSecure’s CRYSTAL-1000C post-quantum cryptographic IP on QuickLogic’s eFPGA Hard IP built for the Intel 18A process node. The results demonstrate that designers can combine hardware performance with flexibility to update cryptographic functionality in the field as standards evolve.
Unlike fixed-function security engines, embedded FPGA (eFPGA) technology enables cryptographic implementations to be updated through a new bitstream rather than requiring costly silicon re-spins. This allows designers to support evolving algorithms, update security implementations, and extend the useful life of their devices.
For applications with long deployment cycles, including aerospace and defense, industrial, communications, and high-performance computing, this level of crypto-agility can help protect investments while preparing for the post-quantum era.
Learn More
QuickLogic and PQSecure have published a technical trade study that explores the implementation in more detail, including the design approach, implementation methodology, and key engineering considerations for integrating reprogrammable post-quantum cryptography into future SoCs.
Download the free trade study to learn how eFPGA Hard IP can enable crypto-agile hardware security without sacrificing performance or requiring costly silicon re-spins.
