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QuickLogic Timeline

QuickLogic Timeline


  • aiSensing deployed a highly successful end-point AI vibration sensor using the SensiML Analytics Toolkit and QuickLogic’s EOS S3
  • Announced a disaggregated, flexible eFPGA chiplet template with eTopus
  • Partnered with Intrinsic ID to provide eFPGA security solutions
  • SensiML delivered new AI accelerator core support for Silicon Labs MG24 and BG24 Series 2 Bluetooth® Wireless SoCs.
  • Added GlobalFoundries 22FDX Process to its growing list of Australis IP Generator-Based eFPGA IP
  • SensiML added AI capabilities to Arduino Nicla Sense ME featuring Bosch Sensortec sensors
  • Delivered eFPGA IP for TSMC 22nm process from Australis IP Generator
  • Announced the first Rad-Hard eFPGA IP for SkyWater RH90 process
  • SensiML teamed with Infineon to provide a complete AI/ML solution for PSoC™ 6 MCUs and a wide range of sensors


  • Launched SensiML open source initiative to assert leadership for commercial AI adoption of smart sensing IoT applications
  • Announced an Amazon-qualified reference design for hearables or battery-powered applications to communicate directly with Alexa
  • Joined DARPA Toolbox Initiative to provide Mil/Aero/Defense Grade Programmable Logic
  • Joined the newly formed Open Source FPGA Foundation as founding and premier member


  • Launched QuickLogic Open Reconfigurable Computing (QORC) Initiative with 100% open source hardware and software support for EOS S3 MCU+eFPGA becoming 1st Programmable Logic company to embrace open source tools
  • Introduced Qomu, an open source hardware dev kit that fits in a USB Type-A slot, enabling portability and development anywhere
  • Announced the availability of eFPGA technology on 28nm FD-SOI process and also became a member of the Samsung SAFE™ IP Partner Program


  • Announced the strategic partnership with SiFive & the launch of SoC templates
  • Launched EOS S3AI SoC Platform for Time Series IoT Endpoint Applications
  • Acquired SensiML SaaS AI Company


  • Announced the availability of eFPGA on TSMC 40nm Process
  • ArcticPro 2 eFPGA IP available for the GLOBALFOUNDRIES 22FDX® (FD-SOI) process
  • Introduced comprehensive QuickAI Platform for Edge & Endpoint AI Applications


  • Established eFPGA Support Center in Taiwan to Accelerate IP Licensing Model


  • Introduced ArcticPro eFPGA on GLOBALFOUNDRIES 65nm and 40nm process
  • Joined GLOBALFOUNDRIES FDXcelerator(TM) Partner Program


  • ArcticLink 3 S2 ultra-low power sensor hub released, offering mobile OEMs significantly increased processing and storage abilities with low power consumption


  • ArcticLink 3 S1 ultra-low power sensor hub announced, offering mobile OEMs always-on context awareness
  • PolarPro 3 announced, QuickLogic’s first reprogrammable logic device for mobile and industrial markets


  • ArcticLink III BX display interface bridge announced, offering OEMs a low-cost, flexible solution for bridging displays with mobile processors


  • ArcticLink III VX announced, combining display bridging with visual enhancement and power savings technologies
  • VEE HD+ and HD+ announced, extending the high-quality display experience and battery life savings for smartphones and tablets with up to FullHD 1,920 × 1,200 displays


  • ArcticLink II VX display bridge announced, introducing Visual Enhancement Engine and providing a high-quality display experience with 25% average battery life extension for smartphones


  • Announced PolarPro II FPGA, designed to meet the connectivity, intelligence, security and system logic requirements for mobile applications


  • CSSP Solutions customer engagement model announced; innovative hardware + software solution for mobile and industrial customers


  • Introduction of first SoC (MCU + eFPGA)


  • October 15 – Initial Public Offering on Nasdaq


  • Introduction of first standard product with eFPGA


  • Open Tool Synthesis introduced


  • Introduction of market’s highest performance, lowest power FPGAs


  • Founded by three of the early inventors of the programmable logic industry, John Birkner, Andy Chan, HT Chua
  • Introduction of ViaLink technology

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