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Introducing the EOS™ S3 Sensor Processing Platform 


The World’s Most Advanced Sensor Processing System

The new EOS S3 sensor processing platform is a multi-core system that enables a vast array of concurrent, MIPS-intensive sensor applications from rudimentary to computationally demanding, MIPS-intensive, algorithms on smartphone, wearable, and Internet of Things (IoT) devices

EOS S3 Sensor Processing Platform

Ideal for Smartphone, Wearable, and IoT Devices

 

This ultra-low power, processing-efficient system enables OEMs to extend battery life while designing in sophisticated, always-on sensing capabilities on mobile devices.  Advanced sensor algorithms such as voice triggering, motion compensated heart rate monitoring, and indoor navigation can be achieved at significant power reduction compared to competing MCU-based solutions.

Unlike traditional MCU-based solutions, the EOS S3 is a multi-core, sensor processing system that enables sophisticated algorithm partitioning to facilitate the lowest possible power consumption for the designated task.

The EOS S3 employs not only fundamental, but also very sophisticated, always-on, context-aware sensing capabilities while staying well within the strict power budgets of smartphone, wearable, and IoT designs. 

Features

32 kHz Oscillator with Real-Time Clock (RTC)

  • 32 kHz crystal oscillator (external crystal required) with bypass option
  • 1 Hz clock generation with compensation register
  • RTC function with one alarm register
  • Start time of 350uS

High Frequency Clock Source

  • Programmable frequency (2 MHz to 80 MHz)
  • Calibrated output (using 32 kHz input)
  • Startup time of  410 µs
  • Clock divider can be programmed in  12 bits

P ower Management Unit

  • Low-power mode with fast wake-up
  • Programmable power modes (deep sleep, sleep with retention, and active)
  • Multiple power domains
  • Power sequencing for sleep and wake-up entry and exit
  • Wake-up triggers via internal and external events
  • Internal LDO support

M4-F Subsystem

  • Cortex M4-F controller with floating point unit (M4-F)
  • Embedded SRAM (up to 512 KB) for code and data memory
  • Vectored interrupt support
  • Wakeup interrupt controller
  • 2-pin SWD port

FFE

  • 50 KB control memory
  • 16 KB data memory
  • Single cycle MAC

Packet FIFOs Batching Memory

  • Multiple packet FIFOs to support the FFE to application 
    processor/M4-F data transfers:
    • 8 KB packet FIFO with ring-buffer mode support
    • 256 x 32 packet FIFO and two 128 x 32 packet FIFOs
  • 128 KB of M4-F SRAM can be used as HiFi sensor batching memory

System DMA

  • 16 channels of DMA allows efficient data movement between processing elements

SPI Slave

  • SPI slave application processor communication of up to 20 MHz

Time Stamping

  • Automatic hardware time stamp on every sensor read in the interrupt mode
  • Up to eight sensor interrupt captured time-stamps (8-bit)
  • Main time stamp of 24-bits
  • Resolution of 1 msec

C Master and Configurable I² C/SPI Interface

  • C master and SPI master with programmable clock pre-scaler
  • Option to disable multi-master support and slave-inserted wait for shorter SCL cycles
  • Configurable for two I² C Masters or  one I² C Master and one SPI Master

Other Interfaces

  • SPI master for interfacing with serial flash memories and other external SPI-based peripherals of up to 20 MHz

Digital Microphone Support

  • I²S microphone

  • PDM microphone

  • Integrated LPSD

UART

  • Serial support for M4-F debug and code development
  • Communication with UART-based external peripherals

Other Peripherals

  • Timers

  • Watchdogs

  • GPIO controllers

ADC

  • Low sampling rate  SD  12-bit

LDOs

  • On-chip LDO for system logic

  • Separate on-board LDO for memory

Programmable Fabric

  • 2-pin SWD port for access to the following memory mapped resources:
    • M4-F internal registers and memories 
    • FFE and Sensor Manager memories
    • FFE control registers
    • Programmable fabric memories
    • Programmable fabric designs through generic AHB bus
    • All memory map peripherals such as timers, WDT, SPI master, etc.
    • I²C master used for I2C sensor debug
    • Multiplexed dedicated parallel debug interface

Packaging Options

  • 42-ball WLCSP (2.7 mm x 2.4 mm x 0.7 mm) (28 user I/O, 2 VCCIO banks)

  • 64-ball BGA (3.5 mm x 3.5 mm x 0.8 mm) (46 user I/O, 2 VCCIO banks)

OS Support

The EOS S3 sensor processing platform is fully compatible with Android OS and RTOS versions.

Key Benefits

 

Ultra-Low Power Operation

The lowest power sensor processing system on the market, the EOS S3 is capable of running fundamental algorithms as well as the most computational-intensive algorithms on the market today, with extra capacity in anticipation of future software requirements.

eos benefit graph

 

Computational Efficiency

The EOS S3 employs QuickLogic’s proprietary Flexible Fusion Engine (FFE), an ARM Cortex M4-F MCU, and programmable logic with partitioning capability to provide the most efficient processing capability for the task at hand.  Routine and less computationally intensive algorithms can be handled in the FFE with a powered-down M4-F.

 

Flexibility

Reprogrammable fabric provides the capability to incorporate and modify customer application-specific logic on the fly, as often as required.

 

Optimized Voice Processing

By integrating dedicated logic for Sensory’s Low Power Sound Detector, and support for I²S and PDM digital microphones, the EOS S3 platform has been optimized for always-on, always-listening voice recognition applications at the absolute lowest power.  In fact, the total average power for voice recognition - including the power of a digital microphone - is less than 1 mA- as measured at the battery.

 

Comprehensive Integrated Solution

QuickLogic offers a full suite of sensor fusion algorithms for incorporation with the EOS S3 system. Customers can also employ their own or 3rd-party algorithms with our advanced Integrated Development Environment (IDE).

EOS Block Diagram

eos block diagram ffe 20 MHz µDSP-like processor for always-on, real-time sensor data
eos block diagram sensor manager Autonomously handles management and control of all sensors
eos block diagram fpga Allows implementation of additional FFE and other customer-specific logic functions
eos block diagram voice

Digital microphone interfaces and Low Power Sound Detector* (LPSD)

* LPSD optimized for Sensory TrulyHandsFree™ Voice Control
eos block diagram arm 80 MHz and up to 512 KB SRAM for general purpose processing and running O/S
eos block diagram serial IO SPI Master/Slave, I²C, UART
eos block diagram system DMA, Integrated RTC, Oscillator, ADC and LDO

Smartphone Application

EOS S3 Smartphone Application Diagrams

Wearable Band Application

EOS S3 Wearable Band Application Diagrams

Amazon Alexa-compatible wearables reference design using Voice-over-Bluetooth Low Energy

The reference design combines QuickLogic’s EOS S3 Sensor Processing SoC, which features an ARM® Cortex™ M4F-powered multicore sensor processing SoC that enables a vast array of sensor applications for smartphones, wearables, hearables and IoT devices, with Nordic’s nRF51822 multiprotocol BLE SoC. The reference design is the first commercially available product to support voice-over- Bluetooth LE connectivity with Amazon Alexa.

This design…

  • Employs Nordic’s nRF51822 SoC to wirelessly stream audio data to an Amazon Alexa smartphone application
  • Supports voice-over- BLE connectivity with Amazon Alexa
  • Enables connectivity to the Alexa App on a Bluetooth 4.0 (and later) smartphone using a custom BLE Audio Profile via the nRF51822 SoC
  • Consumes only 640 microwatts of power (in a typical use case) for always-on listening and ”Alexa” wake-word detection
  • Supports the seamless transmission of voice-over- Bluetooth LE, via a custom application developed by QuickLogic using Nordic’s nRF5 development tools

Have a Question?

If you have questions for our solution experts, please contact us!