With QuickLogic’s Australis eFPGA IP Generator, and the evaluation results from running Aurora, customers can customize and specify the architecture without being restricted to a pre-defined fixed tile implementation.
The Aurora 2.1 Development Tool Suite is based on fully open-source implementation for scalability, longevity, and full code transparency. It supports all major development languages including Verilog, System Verilog and VHDL.
The netlist generated by the synthesis tool is available within Aurora to run the implementation flow. Tools such as Packer, Placer and Router, which are extremely important to meeting the performance requirements of the eFPGA, are optimized for better quality of results. The efficient algorithms of our P&R tools cater well to the critical eFPGA requirements for high performance and efficient area utilization.
Aurora’s enhanced GUI makes it easy for designers to debug and gain a better understanding about the design and its placement, routability, and more. Aurora’s Physical Viewer provides ease-of-use options to the eFPGA user, which makes it easier to understand how the design is being mapped to the eFPGA fabric.
Aurora’s STA and Power Analysis tools provide timing and power information for the design. The STA tool allows the user to navigate through various timing paths that the user can optimize for better timing.
Aurora generates post-layout files that can be used to verify the functionality and timing in any industry-standard simulator such as Questa, Active-HDL, NC-Sim, and VCS, or other open-source simulators.