eFPGA User Tools
The Aurora 2.1 Development Tool Suite is based on a fully open-source implementation for scalability, longevity, and full code transparency.
Contact Sales
Introduction
The Aurora 2.1 Development Tool Suite allows developers to evaluate and/or design with QuickLogic’s Australis-generated eFPGA IPs. It is based on fully open-source synthesis (Yosys), Versatile Place and Route (VPR), and bitstream generation (OpenFPGA) software.
Features
- Open-source components provide full inspectability and ensures device longevity
- Enables evaluation of different FPGA architectures using QuickLogic’s definition files
- Includes support for tcl/tk and GUI through the open-source FOEDAG interface Supports multiple hardware description languages
- Includes evaluation, definition and implementations tools
- Supports Linux Ubuntu, and other versions of Linux through Docker, Podman container, and Windows 10/11
Benefits
- Simplified Evaluation - Supports quick and easy evaluation of eFPGA technology for SoC applications
- Architectural Trade-Offs - Ensures that the generated eFPGA IP has the optimal amount of logic (LUTs), BRAM, and DSP blocks to meet each customer’s unique eFPGA requirements
- More Transparency – Because Aurora is based on open source, the code is highly inspectable, enabling continuous improvement by the development community
- Flexibility – Publicly auditable code leads to higher quality software and allows for the merit-based addition of features by the community, as well as the option to make enhancements that suit each customer’s needs
- Future-Proof – Aurora uses readily available open-source components that the broader community is actively improving upon. With access to source code, the user has ultimate control of the future
QuickLogic Custom Architecture
With QuickLogic’s Australis eFPGA IP Generator, and the evaluation results from running Aurora, customers can customize and specify the architecture without being restricted to a pre-defined fixed tile implementation.
Modifications include:
- CLB(LUT) sizes columns and rows
- Number of columns for BRAM and DSP
- Optimizations for Area/Power or Performance
Integration with Yosys HQ (TabbyCad) Open-Source Synthesis Tool
The Aurora 2.1 Development Tool Suite is based on fully open-source implementation for scalability, longevity, and full code transparency. It supports all major development languages including Verilog, System Verilog and VHDL.
Implementation Flow
The netlist generated by the synthesis tool is available within Aurora to run the implementation flow. Tools such as Packer, Placer and Router, which are extremely important to meeting the performance requirements of the eFPGA, are optimized for better quality of results. The efficient algorithms of our P&R tools cater well to the critical eFPGA requirements for high performance and efficient area utilization.
Physical Viewer and Enhanced GUI
Aurora’s enhanced GUI makes it easy for designers to debug and gain a better understanding about the design and its placement, routability, and more. Aurora’s Physical Viewer provides ease-of-use options to the eFPGA user, which makes it easier to understand how the design is being mapped to the eFPGA fabric.
STA and Power Analysis Tools*
Aurora’s STA and Power Analysis tools provide timing and power information for the design. The STA tool allows the user to navigate through various timing paths that the user can optimize for better timing.
Simulation
Aurora generates post-layout files that can be used to verify the functionality and timing in any industry-standard simulator such as Questa, Active-HDL, NC-Sim, and VCS, or other open-source simulators.
