ArcticPro offers these benefits
Provides a platform to capture more market share during the product introduction stage of silicon and increase the longevity of your product
Greatly facilitates faster time-to-market
Improves system performance and lowers power consumption
Enhances the capabilities of an SoC
Why Embedded FPGA
Block Diagram
eFPGA Use Case – Microcontroller Sensor Hub An always-on sensor hub requires precise timing for sensor data acquisition, and a lot of calculations—a task that is better handled by hardware than software. In this use case, the eFPGA can be used to run sensor fusion at a very low power level, while letting the main CPU sleep until relevant fused data is available.
Product Options – 65nm |
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| Foundry | Process | Device Type | Architecture | Available Array Sizes | # of RAM bits | # of Logic Cells | # Flip Flop&& | # GPIO | |||||||||||
| TSMC | 65nm LP | SVT | ArcticPro | 32x32 | 73,728 (RAMFIFO) | 1019 | 1019 (LC) 384 (IO) | 128 | |||||||||||
| GF | 65nm LPE | HVT, SVT | ArcticPro | 32x32 | 73,728 (RAMFIFO) 135,168 (ASSP) | 1019 | 1019 (LC) 1019 (LC) 264 (IO) | 88 | |||||||||||
&&LC + PREIO register paths
**with die seal + scribe line
Custom array sizes, process and device types available
Product Options – 40nm |
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| Foundry | Process | Metal Layers | Available Array Sizes | # of Logic Cells | # Flip Flop | # Interface signals&& | |||||||||||||
| GF | 40nm LP | 5 | 32x32 | 1019 | 1019 (LC) 192 (IO) | 64+768 (A2F%) 128+1536 (F2A%) 256 (DEF) |
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| TSMC | 40nm ULP | 5 | 32x32 | 1019 | 1019 (LC) 192 (IO) | 64+768 (A2F%) 128+1536 (F2A%) 256 (DEF) |
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&&LC + PREIO register paths
%(reg) + (combinatorial)
*Based on APB 40MHz clock
eFPGA USE CASE – FITNESS BAND SoC
eFPGA USE CASE – SENSOR HUB SoC
ArcticPro offers both the lowest power consumption on the market, with standby currents as low as 30uA in a 1000 logic cell configuration, and also boasts the most area utilization-efficient FPGA architecture.
Silicon that is based the ArcticPro architecture has been in mass production for more than seven years. It’s currently available in 65nm and 40nm implementations, and is portable to any other process node, and sizes ranging from 64- to 4K logic cells implementations.
The logic cell architecture of the ArcticPro Ultra-Low Power Embedded FPGA (eFPGA) IP offers unprecedented flexiblility that allows for very high utilization. We call this “fine grain” architecture because it has multiple outputs per logic cell, allowing the logic cell to be utilized as a 4-input Look Up Table (LUT), or as two independent 3-input LUTs, or a high fan-in 8:1 multiplexer. In addition, an independent register and a 2-input multiplexer is also available. Based on real user designs, the logic cell is equivalent to 3.5x the utilization of a standard 4-input LUT architecture.
Partners
GLOBALFOUNDRIES®
QuickLogic's partnership with GLOBALFOUNDRIES® adds a unique dimension to the FDX program by offering customers ultra-low power embedded FPGA (eFPGA) Intellectual Property, complete software tools and a compiler.
https://www.globalfoundries.com/services/fdxcelerator
Alliance: https://www.smics.com/en/site/design_maturity
Mentor®, a Siemens Business
QuickLogic’s partnership with Mentor enables designers to have a seamless design and development environment for eFPGA technology. Mentor’s synthesis tool Precision is optimized for QuickLogic’s ArcticPro eFPGA architecture. Working in conjunction with QuickLogic’s Aurora software, the Mentor tool helps designers generate high performance designs for eFPGA applications.
https://www.mentor.com/products/fpga/synthesis/
Aldec, Inc.
QuickLogic’s partnership with Aldec for Simulation flow helps designers verify their eFPGA designs using Aldec’s Active-HDL software. Taking advantage of simulation expertise from Aldec, designers implementing QuickLogic’s eFPGA technology can be successfully complete design verification for functionality and performance using the Aldec simulation environment.
https://www.aldec.com/en/products/fpga_simulation/active-hdl
